/Width 38 Programmable VLIW and SIMD Architectures for DSP and Multimedia Applications Deepu Talla Laboratory for Computer Architecture Department of Electrical and Computer Engineering The University of Texas at Austin deepu@ece.utexas.edu Abstract – Digital Signal Processing (DSP) and multimedia workloads are expected to be /W 435 /Length 11 0 R The next segment concentrates on real-life examples of VLIW implementations. (VLIW) processors. CEVA Inc. Technology is removing the gap between embedded and VLIW computing: high-performance methods that seemed too costly for embedded use have become feasible … VLIW Tutorial Summary: The project is centered around a multi-part VLIW tutorial. • change in the instruction set architecture, i.e., 1 program counter points to 1 bundle (not 1 operation) • want operations in a bundle to issue in parallel • fixed format so could decode operations in parallel • enough FUs for types of operations that can issue in parallel • pipelined FUs Autumn 2006 CSE P548 - VLIW 2 VLIW Processors Department of ECE Laboratory for Computer Architecture SIMD Processors • Single Instruction Multiple Data • Exploit data parallelism as opposed to instruction parallelism in VLIW processors • A technique that has been added to general-purpose processors for DSP and multimedia processing > Intel’s MMX, Sun’s VIS, Motorola’s AltiVec Very long instruction word refers to instruction set architectures designed to exploit instruction level parallelism. /D [ 1 0 ] An efficient motion-adaption de-interlacing technique on VLIW DSP architecture. Such an irregular processor poses many challenges in the construction of its compiler. 1 1 1 rg 36 36 540 720 re f BT 563.25 42.75 TD 0 0 0 rg /F0 12 Tf 0 Tc 0 Tw (1) Tj -342 27.75 TD /F0 9.75 Tf 0.1138 Tc -0.0513 Tw (\251 1999 Berkeley Design Technology, Inc.) Tj 14.25 654.75 TD /F0 12 Tf -0.0637 Tc 0.3137 Tw (VLIW Architectures for DSP) Tj ET 1 1 1 rg 126 417.75 360 270 re f q 326.25 0 0 54.75 152.25 597.75 cm 0.502 0.502 0.502 rg BI VLIW Architecture - Basic Principles. u 16-bit fixed-point VLIW DSP core from Lucent/Motorola u StarCore claims it's a scalable architecture l First VLIW machine to target low-power apps u More execution units (13) than 'C62xx (8), but fewer instructions can be issued per cycle l Six for SC140 vs eight for 'C62xx 7 0 obj ,�v� .>?��K�x]F 1�U"˂h�����8O�. It is more difficult to program a parallel system than a single processor system, as the architecture of different parallel systems may vary, and the processes of multiple processors must be synchronized and coordinated. %PDF-1.2 /Subtype /Image Very long instruction word or VLIW refers to a processor architecture designed to take advantage of instruction level parallelism This type of processor architecture is intended to allow higher performance without the inherent complexity of some other approaches. 2"�zϺ2��c�[Pi�x�^��18�`��'�`�y\���]Rl�aO��HU�n�O�ļ��/ó�������G�$���x���4Ѿ+'��{�o���2�~4 ��ǣowv����%���������C'c���Z���'�g���gˇV����+� '>;9�9ti���N-�i��A1S %���� grained parallelism of DSP applications is the very long instruction word (VLIW) architecture. Q q 326.25 0 0 54.75 149.25 600.75 cm 0.0471 0.0039 0.7137 rg BI stream Multi-ported memory , VLIW architecture, Pipelining , Special Addressing modes in P- DSPs , On chip Peripherals, Computational accuracy in DSP processor, Von Neumann and Harvard Architecture, MAC UNIT 2 : ARCHITECTURE OF TMS320C5X (08) Commercial VLIW CPUs include: 1. /ColorSpace /DeviceRGB The Gen4 CEVA-XC unifies the principles of scalar and vector processing in a powerful architecture, enabling two-times 8-way VLIW and up to an unprecedented 14,000 bits of data level parallelism. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. The architecture of the LILY processor, a 300-MHz six-way VLIW DSP, has been presented. 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/ColorSpace 2 0 R 1 Introduction The exponentially increasing performance and general-ity of superscalar processors has lead many to believe that VLIW Introduction VLIW: Very Long Instruction Word (J.Fisher) multiple operations packed into one instruction each operation slot is for a fixed function constant operation latencies are specified architecture requires guarantee of: –parallelism within an instruction => no x­operation RAW check –no data use before data ready => no data interlocks Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs. 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